This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the subject matter described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, not as admissions of prior art.
The present disclosure relates generally to non-volatile memory devices and, more specifically, to techniques for reducing unintended or otherwise unwanted programming events (e.g., a write) in the operation of such non-volatile memory devices.
Solid state non-volatile memory devices are widely used today in many electronic systems and have continued to experience high growth in recent years. This is attributable, at least in part, to the capability of non-volatile memory for long-term persistent data storage. For instance, when compared to volatile memories, such as dynamic random access memory (DRAM) which typically loses stored data almost immediately when power is removed, non-volatile memory does not require a power source to retain stored information. For example, some non-volatile memory devices are capable of retaining data on the order of many years.
Non-volatile memory arrays may include bit cells arranged in rows and columns, similar to that of volatile memory. A common type of non-volatile memory bit cell utilizes a floating gate transistor to store a data state. In general, floating gate transistors are similar to conventional MOSFET transistors in structure, but include an additional gate element that is electronically isolated, hence the term “floating gate.” The floating gate acts as a storage element for the bit cell. By way of background, a conventional non-volatile memory cell 10 that utilizes a floating gate transistor is shown in FIG. 1. The memory cell 10 shown here includes a single floating gate transistor with its drain (D) connected to a bit line (BL) and its control gate connected to a word line (WL). A floating gate element (FG) is physically disposed between the control gate (CG) and the channel region, and is electrically isolated, such as by a thin dielectric film, from the control gate, source, and drain. Examples of non-volatile memories based on floating gate transistors in FIG. 1 include electrically erasable programmable read only memory (EEPROM) and flash memory.
Memory cells of this type typically have two states, a “programmed” state and an “erased” state. The amount of charge trapped on the floating gate determines the state of the cell and may be controlled through program and erase operations. For example, the cell may be programmed by biasing the cell so that electrons tunnel through the thin dielectric film isolating the floating gate causing it to become negatively charged. This has the effect of increasing the threshold voltage of the transistor by shielding the channel region from the control gate so that when a read voltage is applied to the control gate, current does not conduct between the source and drain, thus corresponding to a logical 0. In an erase operation, the memory cell is biased to release electrons trapped in the floating gate. The absence of trapped electrons on the floating gate when the read voltage is applied allows for current to conduct between the source and drain, thus corresponding to a logical 1. Depending on the construction of the transistor, the tunneling mechanism may be Fowler-Nordheim (FN) tunneling or hot-carrier injection. While FIG. 1 shows a basic type of floating gate transistor, other floating gate transistor designs have since been developed. Thus, the specific physical arrangement of the floating gate relative to the other elements of the memory cell can vary depending on the particular design. Nonetheless, most floating gate transistor designs will generally operate on the concept that the amount of charge on the floating gate determines the logical state of the memory cell.
In the semiconductor industry, there is generally a continuing effort to reduce the overall size of semiconductor circuits. This is because smaller devices tend to have a competitive advantage in the market over larger counterparts, as smaller devices tend to operate more efficiently (e.g., lower power requirements), use less circuit area, and are less costly to manufacture. In accordance with this trend, the overall size of memory devices is also continuing to decrease. For example, smaller memory arrays may be achieved by using smaller manufacturing process nodes, which scales down the size of the circuitry. Additionally, certain components of memory arrays, such as drivers and sensing circuitry, may be designed such that they are shared more effectively, thus requiring fewer such components. Both techniques are frequently used to achieve increasingly smaller dimensions.
As the overall size of memory devices continues to decrease in accordance with this trend, new challenges have also been encountered. For instance, at smaller process nodes, conductive lines and other circuit components are located increasingly closer together, which can sometimes result in unwanted electrical behavior. In some non-volatile memories, it has been observed that under certain conditions, performing an operation on a selected bit cell in the array can sometimes stress nearby bit cells resulting in unintended and unwanted effects, such as unintentionally changing the date state stored by the cell (e.g., from 1 to 0, or vice versa). This occurrence is commonly referred to as a “disturb” event or “disturbance.” For example, a disturbance in a cell that results when programming another cell may be referred to as a “program disturb,” while one that results from reading another cell may be referred to as a “read disturb” and so forth.
Disturbs are particularly problematic in non-volatile memories, as unintended changes to the data state stored in memory cells will result in erroneous data being read from those cells. Accordingly, the incorporation of disturb management techniques into memory devices that help to reduce the occurrence of disturbs are particularly useful.